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The full name for this chip is the AVG Gate Array, formally known as the Vector Generator Stack and PC Processor. Originally designed by Dean Chang. It contained the Program Counter, the Memory File Stack, and the Stack Counter.
More functional descriptions by Jed Margolin in “The Secret Life of Vector Generators” are found below:
“The gate array is designed to be the Stack/Stack Jointer and Program Counter for the analog vector generator circuit used in vector type games. The Program Counter (PC) has 14 Bits with Carry Out. The Stack is three levels deep and stores the upper thirteen bits (AVGI – AVGI3) of the Program Counter. (Refer to Figure 2). When the gate array receives control signals from the analog vector generator it executes the JMP, JSR, and RTS Instructions. See attached detail timing diagrams for proper operation. The normal gate array operation is an Increment PC (INC PC) operation which is controlled by ST3 and ST2 signals supplied by external hardware. For the JMP Instruction, /STROBE_2 loads the PC with address data on DVYO- DVY12. For the JSR Instruction, /STROBE_O stores the current PC data onto the Stack, /STROBE_1 Increments the Stack Pointer and /STROBE_2 Loads the PC with DVYO – DVY12 data. For the RTS Instruction, /STROBE_1 Decrements the Stack-Pointer and /STROBE_2 Loads the PC from Stack Outputs. ST2 (LOW) Enables normal Increment PC operation. On the next rising edge of ST3, AVGO will go back to HIGH. The rising edge of AVG0 will increment PC’s AVG1 – AVGI3 outputs.
The Stack Pointer is designed to count in the 0, 1, 2, 0, 1, 2 … etc. sequence, however, since power on can cause the Stack Pointer value to be 3, it is recommended that a “dummy” JSR Instruction be generated before using a real JSR Instruction.
The vector generator circuit has nine instructions with each instruction consisting of either 2 bytes or 4 bytes of data. The op-code field of each instruction resides in the second byte. Since the op-code must be fetched before any instruction parameter field, the Program Counter was specifically designed with AVG0-AVG13 following a 1, 0, 3, 2, 5, 4 … etc. count sequence. During an instruction op-code fetch cycle, AVG0 is HIGH. After an instruction op-code is fetched, ST2 goes LOW which causes AVG0 to go LOW after the next ST3 clock. This allows the vector generator to fetch the Instruction parameters for current instruction. As long as AVG0 is LOW, the next ST3 clock will bring AVG0 back to HIGH. This LOW to HIGH AVG0 transition will increment AVGI – AVGI3 and consequently the Program Counter will be ready for the next instruction fetch.
Star Wars was field tested around May 1983 and went into production in July. The Star Wars AVG had Linear Scaling and the AVG Gate Array.
There was something different about the AVG, though.
In order to have the Death Star explode the way we wanted it to, it wasn’t enough to draw lots of concentric circles. We wanted to defocus the beam to fill it in. We briefly considered adding a vacuum tube to the monitor to control the Focus Voltage. Fortunately, the lead time for the part was too long. So what I did was to give the Vector Generator the ability to overdrive the monitor’s color inputs. Overdriving the inputs causes the CRT to draw more current than it normally uses and drags down the High Voltage., which changes the normal ratio of Focus Grid voltage to Anode voltage, which defocuses the beam. This relationship is explained in The Secret Life of XY Monitors.”
These chips don’t go bad often, but when they do, you will see errant images, 3D lines that don’t look right, weird looking tie fighters, and sometimes the game just won’t boot at all.
If you suspect you are having AVG chip issues, replace your OEM part with our high quality modern improved version for years of reliable game play.
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